High performance W-CDMA slot synchronisation for initial cell search with reduced hardware

ABSTRACT

Two preferred embodiments provide slot synchronization of an initial cell search. Two Finite Impulse Response (FIR) filters are used to correlate the synchronization codes transmitted in the downlink (forward link). A sign bit is taken after the first FIR to significantly reduce the hardware requirements for the second FIR, and thus the whole system. The correlated results from the second FIR can be further processed using two different algorithms. The first adds a square operation to the correlated results whilst the second takes the magnitude before passing to the next stage. Regardless of which algorithm is adopted, the results are accumulated (I and Q), instead of averaged, and stored in a memory location for each successive correlation over the same location in different slots. The physical-layer processor (PLP) then reads the accumulated results from the memory location and searches for the peak position corresponding to the slot boundary.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a 3GPP (3^(rd) Generation PartnershipProject) W-CDMA (Wideband Code-Division Multiple Access) FDD (FrequencyDivision Duplex) mode system, and more particularly to a method for slotsynchronisation for an initial cell search, both in terms of performanceand resource requirements of the system.

BACKGROUND OF THE INVENTION

The following abbreviations are hereinafter employed in thespecification, as are other standard industry terms:

3GPP 3^(rd) Generation Partnership Project AWGN Additive White GaussianNoise BS Base Station CPICH Common Pilot Channel DL Downlink FDDFrequency Division Duplex FIR Finite Impulse Response H/W Hardware IIn-phase PAR Peak-to-Average Ratio PSC Primary Synchronisation Code PLPPhysical Layer Processor Q Quadrature-phase SSC SecondarySynchronisation Code SCH Synchronisation Channel SR Shift Register UEUser Equipment W-CDMA Wideband Code-Division Multiple Access

When UE is powered on, the UE has no knowledge of the system timing of atransmitting cell. The 3GPP W-CDMA FDD standard specifies an initialcell search procedure to synchronise the UE reception timing to that ofthe serving cell.

The initial cell search procedure includes three steps, namely: slotsynchronisation; frame synchronisation and codegroup identification; andscrambling-code identification.

Generally, the goal of slot synchronisation is to obtain the slot timingreference by analysis of synchronisation sequences transmitted in eachcell by the system. Frame synchronisation and codegroup identificationis used to determine the transmitting frame boundary as well as thecodegroup to which the primary scrambling code belongs. Scrambling-codeidentification is used to identify the primary scrambling code used bythe base station (BS) to transmit a common pilot channel (CPICH).

The Synchronisation Channel (SCH), being the synchronisation sequence,is a downlink signal that consists of two sub-channels, the Primary andSecondary SCH. The 10 ms radio frames of the Primary and Secondary SCHare divided into 15 slots, each having a length of 2560 chips. FIG. 1illustrates the general structure of the SCH radio frame. The primarysynchronisation code (PSC) is the same for each cell, and the secondarysynchronisation code (SSC) is different for each cell. PSC is intendedto achieve slot synchronisation whilst SSC is adopted to achieve framesynchronisation.

The first step in the baseband for the UE to synchronise to the servingcell is to perform an initial cell search. There are altogether threesteps in a cell search procedure. This invention is directed towards thefirst step of the cell search, namely slot synchronisation.

The principle used in slot synchronisation is to perform correlationover the received PSC. This correlation is repeated for as long as thelength of a slot, i.e., 2560 chip duration. A profile of 2560 locationsin a slot is then constructed. By determining the peak of the profile,the slot boundary can be determined.

Examination on the PSC sequence suggests that a FIR of length 256 isnecessary to perform the correlation. However, such an FIR requires alarge piece of hardware for realisation. In order to reduce the cost ofimplementation, it is necessary to look for other possibilities ofreducing hardware requirements while maintaining acceptable performance.

This identifies a need for a new method of slot synchronisation whichovercomes the problems inherent in the prior art.

DISCLOSURE OF INVENTION

The present invention is directed towards providing a method forachieving improved slot synchronisation.

The present invention seeks to outline two preferred embodiments forslot synchronisation of an initial cell search for Third-GenerationPartnership Project (3GPP) Wideband Code-Division Multiple Access(W-CDMA) Frequency Division Duplex (FDD) mode system. Two Finite ImpulseResponse (FIR) filters are used to correlate the synchronisation codestransmitted in the downlink (forward link). Sign bit is taken after thefirst FIR to significantly reduce the hardware requirements for thesecond FIR, and thus the whole system. The correlated results from thesecond FIR can be further processed using two different algorithms. Thefirst is to add a square operation to the correlated results whilst thesecond is to take the magnitude before passing to the next stage.Regardless of which algorithm is adopted, the results are accumulated,instead of averaged, and stored in a memory location for each successivecorrelation over the same location in different slots. Thephysical-layer processor (PLP) then reads the accumulated results fromthe memory location and searches for the peak position. This peakposition corresponds to the actual slot boundary. Note that the I and Qbranches are processed independently and the profiles are combined usingaccumulation for system performance improvement.

The present invention seeks to provide a method for slot synchronisationfor an initial cell search, using two finite impulse response (FIR)filters, the method including the steps of:

-   -   synchronisation hardware of the user equipment (UE) receiving an        I and a Q signal;    -   simultaneously calculating the results from a first FIR for the        I and Q signals;    -   simultaneously obtaining the sign bit after the first FIR for        the I and Q signals;    -   simultaneously calculating the results for the second FIR for        the I and Q signals;    -   processing the second FR for the I signal and the second FIR for        the Q signal using an algorithm, thereby providing accumulated        results;    -   storing the accumulated results from the algorithm in a memory        location;    -   successively processing the second FIR for the I signal and the        second FIR for the Q signal according to the algorithm, over the        same location in different slots and storing the successive        accumulated results in the memory location; and    -   a physical-layer processor (PLP) reading the successive        accumulated results from the memory location and searching for        the peak location which corresponds to the actual slot boundary.

The present invention according to one aspect seeks to provide that thealgorithm includes: determining the square of the sum of the componentsof the second FIR for the I signal, and adding this to the square of thesum of the components of the second FIR for the Q signal.

The present invention according to another aspect seeks to provide thatthe algorithm includes: determining the magnitude of the sum of thecomponents of the second FIR for the I signal, and adding this to themagnitude of the sum of the components of the second FIR for the Qsignal.

In accordance with a specific embodiment of the present invention it issought to be provided that the accumulated results are stored in a16-bit memory location to build a profile of 2560 chips in length.

In a broad form, the present invention provides that the successiveaccumulated results are accumulated over n_(s) slots and averaging isnot used.

In a further broad form, the peak location corresponds to the receivedslot boundary.

In accordance with a further specific embodiment of the presentinvention it is sought to be provided that the required hardware at thesecond FIR is reduced due to adoption of the sign bit after the firstFIR.

The present invention according to another aspect seeks to provide thatthe second FIR uses 241 taps.

The present invention according to yet another aspect seeks to providethat the method avoids rounding or truncation error caused by averaging.

The present invention according to still yet another aspect seeks toprovide that the first FIR is reused for the secondary synchronisation.

In a preferred form of the invention a detection probability ofapproximately 96.7% is obtained in an AWGN channel when accumulated over15 slots.

In another preferred form of the invention a detection probability ofapproximately 96.2% is obtained in an AWGN channel when accumulated over15 slots.

In another preferred form of the invention there is provided a methodfor slot synchronisation for an initial cell search, substantially asherein described with reference to the accompanying figures and tables.

BRIEF DESCRIPTION OF THE FIGURES

The present invention will become apparent from the followingdescription, which is given by way of example only, of a preferred butnon-limiting embodiment thereof, described in connection with theaccompanying figures and tables, wherein:

FIG. 1 illustrates the frame structure of a synchronisation channel.This is the frame structure of the SCH transmitted from the BS;

FIG. 2 illustrates a preferred embodiment of the present inventionshowing the architecture of slot synchronisation. This is the hardwarelayout of the implementation of slot synchronisation for an initial cellsearch;

FIG. 3 illustrates the correlation profile after accumulation over 1slot for a preferred embodiment of the present invention. This is thecorrelation profile (2560 positions for 1× sampling) between theincoming DL signals and the PSC code after accumulation over 1 slot forImplementation 1;

FIG. 4 illustrates the correlation profile after accumulation over 5slots for a preferred embodiment of the present invention. This is thecorrelation profile (2560 positions for 1× sampling) between theincoming DL signals and the PSC code after accumulation over 5 slot forImplementation 1;

FIG. 5 illustrates the correlation profile after accumulation over 10slots for a preferred embodiment of the present invention. This is thecorrelation profile (2560 positions for 1× sampling) between theincoming DL signals and the PSC code after accumulation over 10 slot forImplementation 1;

FIG. 6 illustrates the correlation profile after accumulation over 15slots for a preferred embodiment of the present invention. This is thecorrelation profile (2560 positions for 1× sampling) between theincoming DL signals and the PSC code after accumulation over 15 slot forImplementation 1;

FIG. 7 illustrates the correlation profile after accumulation over 30slots for a preferred embodiment of the present invention. This is thecorrelation profile (2560 positions for 1× sampling) between theincoming DL signals and the PSC code after accumulation over 30 slot forImplementation 1;

FIG. 8 illustrates the detection probability vs. acquisition the forvarious numbers of slot accumulations for a preferred embodiment of thepresent invention. This figure shows the detection probability curvesfor various numbers of slot accumulations for Implementation 1. Thedetection probability curves are used to decide the optimum number ofslots needed for accumulation given a certain performance criteria;

FIG. 9 illustrates the correlation profile after accumulation over 1slot for an alternate preferred embodiment of the present invention.This is the correlation profile (2560 positions for 1× sampling) betweenthe incoming DL signals and the PSC code after accumulation over 1 slotfor Implementation 2;

FIG. 10 illustrates the correlation profile after accumulation over 5slots for an alternate preferred embodiment of the present invention.This is the correlation profile (2560 positions for 1× sampling) betweenthe incoming DL signals and the PSC code after accumulation over 5 slotfor Implementation 2;

FIG. 11 illustrates the correlation profile after accumulation over 10slots for an alternate preferred embodiment of the present invention.This is the correlation profile (2560 positions for 1× sampling) betweenthe incoming DL signals and the PSC code after accumulation over 10 slotfor Implementation 2;

FIG. 12 illustrates the correlation profile after accumulation over 15slots for an alternate preferred embodiment of the present invention.This is the correlation profile (2560 positions for 1× sampling) betweenthe incoming DL signals and the PSC code after accumulation over 15 slotfor Implementation 2;

FIG. 13 illustrates the correlation profile after accumulation over 30slots for an alternate preferred embodiment of the present invention.This is the correlation profile (2560 positions for 1× sampling) betweenthe incoming DL signals and the PSC code after accumulation over 30 slotfor Implementation 2;

FIG. 14 illustrates the detection probability vs. acquisition time forvarious numbers of slot accumulations for an alternate preferredembodiment of the present invention. This figure shows the detectionprobability curves for various numbers of slot accumulations forImplementation 2. The detection probability curves are used to decidethe optimum number of slots needed for accumulation given a certainperformance criteria;

Table 1 presents the detection probability and error probability forslot synchronisation for implementation 1;

Table 2 presents the acquisition time and detection probability fordifferent number of attempts for implementation 1;

Table 3 presents the detection probability and error probability forslot synchronisation for implementation 2;

Table 4 presents the acquisition time and detection probability fordifferent number of attempts for implementation 2.

MODES FOR CARRYING OUT THE INVENTION

Overview

Sign-bit correlation provides significantly reduced resourcerequirement. Three methods for adopting sign-bit correlation areconsidered hereinafter. The first is to take the sign bit at the inputto the first FIR. The second is to take the sign bit after the first FIRand before the second FIR and the third possibility is to take the signbit after the second FIR. Other possibilities do not make muchdifference in terms of resource requirements.

The first approach has the lowest hardware requirement but is volatileto the phase shift and deep fading of a mobile communication channel.Therefore, this approach requires a long acquisition time to get areliable slot boundary. The second approach has a slightly higherhardware requirement than the first approach. However, this approach hasthe ability of reducing the effect of phase shift and deep fading bytaking the sign bit only after going through a 16-stage FIR. Therefore,reducing the acquisition time significantly. The third approachbasically does not save significant hardware resources although thethird approach performs the best of the three. Judging from the hardwarerequirements as well as the performance of each approach, the secondapproach seems to have a good balance of these two requirements. In thisconnection, it is chosen to be implemented for the 3GPP W-CDMA FDD modeUE system.

The results after the 2nd FIRs (I and Q) are accumulated to build aprofile of 2560 locations in the memory. For any subsequent resultstaken over more than 1 slot, the results are also simply accumulated toimprove the profile. This operation saves hardware for averaging theresults. After sufficient accumulation, the PLP software reads theprofile from the memory and detect the peak of the profile. This peaklocation corresponds to the offset of the actual slot boundary to theslot boundary where the correlation was started. Consequently, thereceived timing can be adjusted to the actual slot boundary.

Slot synchronisation is achieved by means of detecting the Primary SCH(PSC), which is transmitted at the first 256 chips of each slot. The PSCis the same for every cell in the system. The PSC is modulated on the Iand Q channels with identical real and imaginary components. The PSC isconstructed from a so-called generalised hierarchical Golay sequencewith good aperiodic auto correlation properties.

The PSC is generated by repeating a sequence a modulated by a Golaycomplementary sequence.

The sequence a is given by:a=<1, 1, 1, 1, 1, 1, −1, −1, 1, −1, 1, −1, 1, −1, −1, 1> andb=<a, a, a, −a, a, a, −a, a, a, a, −a, a, a, a>.Therefore, the PSC is defined as:Cpsc=y=(1+j)*bwhere the leftmost chip in the sequence corresponds to the chiptransmitted first in time.Procedure

Two (2) FIR filters are used. The 1st FIR has 16 taps of width 10 bits,whilst the 2nd FIR has 241 (256-15) taps of width 1 bit. Before startingcorrelation, the PLP (shown in FIG. 2) loads the coefficients onto the1st FIR, where the coefficients correspond to the patterns of thea-sequence with the mapping ‘1’ to ‘0’ and ‘−1’ to ‘1’.

A ‘0’ means addition and a ‘1’ means subtraction at the summation block.Similarly, the coefficients for the 2nd FIR follow the pattern of theb-sequence with the same mapping. The coefficients for the 2nd FIR canbe pre-programmed in the design since the flexibility of reusing thisFIR for the secondary synchronisation is not needed. However, thesecoefficients only apply for tap number n×16, wherein n=0 to 15, as shownin FIG. 2.

The incoming signal (I or Q) is fed to the 1st FIR at 1× the chip rate.The sign bit (0 or 1) of the output (chip rate) from the 1st summationblock is input to the 2nd FIR to produce a result from the 2nd summationblock at chip rate. The calculation at the 2nd FIR is merely an XORoperation. The first 255 results from the 2nd FIR are discarded forflushing the FIRs. The same block of hardware is repeated independentlyfor the I and Q branches of the received signal. The output from theindependent I and Q branch are then accumulated and input to theprofile. There are two preferred methods of implementing the A-blockdepicted in FIG. 2.

1) Implementation 1: The sum from the 2nd FIR is squared and added withthe output from the other branch.

2) Implementation 2: The magnitude of the sum from the 2nd FIR is addedwith the output from the other branch.

The end result is stored in a 16-bit memory location to build a profileof 2560 in length. In order to achieve improved performance, the resultis accumulated over n_(s) slots. A counter, which runs from 0 to 2559,is used to keep track of the position in the profile to which theresults should be accumulated and written. This counter starts after 255chips time from the start of the correlation to compensate for theflushing of the FIRs.

Due to the use of sign bit for the output from the 1st FIR, the maximumvalue from the output of the 2nd FIR is ±16.

Calculation 1: After the square operation, the maximum value becomes 256(8-bit unsigned) and this maximum value turns into 512 (9-bit unsigned)after the summation. For 16-bit memory, the maximum number ofaccumulations allowed is 16−9=7-bit, which is equivalent to 128.

Calculation 2: After taking the magnitude, the maximum value becomes 16(4-bit unsigned) and this maximum value turns into 32 (5-bit unsigned)after the summation. For 16-bit memory, the maximum number ofaccumulations allowed is 16−5=11-bit, which is equivalent to 2048.

Therefore, the maximum number of slot accumulations can be up to 128 forimplementation 1 and 2048 for implementation 2 before an overflowoccurs. At the end of the accumulation, the PLP shall read the profilestored in the memory and identify the peak location. This peak locationcorresponds to the received slot boundary.

Simulation Results and Statistics

In the simulation, the parameters given in Table 4-1 of the document 3GTS25.133 v3.2.0 “Requirements for Support of Radio Resource Management(FDD) (Release 1999)”, are used in conjunction with the assumption ofzero frequency error in the receiver.

FIGS. 3 to 7 show simulation results for implementation 1, the squaredcombination.

Since the clock rate is higher than the chip rate (e.g., 8 times), thealgorithm for finding the peak position from the 2560-location profiletypically takes less than 1 slot. It can be assumed that the extra timerequired to start another slot synchronisation, in case the currentsynchronisation is in error (e.g., by checking the PAR), is 1 slot.Therefore, the acquisition time statistics (shown in Table 2) can beconstructed from the detection probability table shown in Table 1.

Let:

r=number of attempts (retries)

P_(d)=detection probability

P_(e)=error probability

t_(a)=acquisition timeP _(e)=1−P _(d)

After r attempts,P _(d)=1−P _(e) ^(r)t _(a) ≈r×(n _(s)+1) slots

From FIG. 8, assuming a desired P_(d) of 95%, n_(s)=15 should be chosen.

FIGS. 9 to 13 show simulation results for implementation 2, themagnitude combination.

Similar to implementation 1, the detection probability, errorprobability and acquisition time for implementation 2 are given in Table3 and Table 4, respectively.

From FIG. 14, assuming a desired P_(d) of 95%, n_(s)=15 should bechosen.

Advantages of the present invention include:

The adoption of sign bit after the 1^(st) FIR reduces hardwaresignificantly at the 2^(nd) FIR. Thus the overall cost should bereduced;

The use of only 241 taps for the 2^(nd) FIR instead of 256 taps helps toreduce the hardware requirement;

The use of sign bit facilitates use of the accumulation instead ofaveraging when the results are written to the memory. This typicallyavoids the possibility of rounding or truncation error caused byaveraging;

Accumulation is used for storing the correlation results instead ofaveraging. This saves hardware for an averaging operation;

The hardware for the 1^(st) FIR can be reused for the secondarysynchronisation since the secondary synchronisation construction issimilar to the primary synchronisation;

Implementation 1 has a detection probability of 96.7% in an AWGN channel(see Table 1) when accumulated over 15 slots. Implementation 2 has adetection probability of 96.2% when accumulated over 15 slots under thesame channel condition as Implementation 1.

Two preferred methods of slot synchronisation for an initial cell searchhave been disclosed. Implementation 1 has a slightly higher hardwarerequirement but improved performance compared to implementation 2.

Thus, there has been provided in accordance with the present invention,a method for slot synchronisation for an initial cell search whichsatisfies the advantages set forth above.

The invention may also be said broadly to consist in the parts, elementsand features referred to or indicated in the specification of theapplication, individually or collectively, in any or all combinations oftwo or more of said parts, elements or features, and where specificintegers are mentioned herein which have known equivalents in the art towhich the invention relates, such known equivalents are deemed to beincorporated herein as if individually set forth.

Although the preferred embodiment has been described in detail, itshould be understood that various changes, substitutions, andalterations can be made herein by one of ordinary skill in the artwithout departing from the scope of the present invention ashereinbefore described and as hereinafter claimed.

1. A method for slot synchronization for an initial cell search, usingfinite impulse response (FIR) filters, the method comprising: receivingan I signal and a Q signal at synchronization hardware of userequipment; calculating first I results and first Q results by FIRfiltering the I and Q signals, respectively; obtaining I and Q sign bitsfrom the first I and Q results; calculating second I results and secondQ results by respectively FIR filtering the I and Q signals using the Iand Q sign bits, respectively; processing the second I results and thesecond Q results using an algorithm, thereby providing accumulatedresults; storing the accumulated results from the algorithm in a memorylocation, successively processing successive FIR filtered second Iresults and successive FIR filtered second Q results according to thealgorithm, over the same location in different slots to obtainsuccessive accumulated results and storing the successive accumulatedresults in the memory location; and reading the successive accumulatedresults from the memory location with a physical-layer processor andsearching for a peak location which corresponds to an actual slotboundary.
 2. A method as claimed in claim 1, wherein the algorithmincludes: determining a value equal to the square of a sum of componentsof the second I results, and adding the value to the square of a sum ofcomponents of the second Q results.
 3. A method as claimed in claim 2,wherein a detection probability of approximately 96.7% is obtained in anAWGN channel when accumulated over 15 slots.
 4. A method as claimed inclaim 1, wherein the algorithm includes: determining a magnitude of asum of components of the second I results, and adding the magnitude to amagnitude of a sum of a components of the second Q results.
 5. A methodas claimed in claim 4, wherein a detection probability of approximately96.2% is obtained in a AWGN channel when accumulated over 15 slots.
 6. Amethod as claimed in claim 1, wherein the accumulated results are storedin a 16-bit memory location to build a profile of 2560 in length.
 7. Amethod as claimed in claim 1, wherein the successive accumulated resultsare accumulated over n_(s) slots and averaging is not used.
 8. A methodas claimed in claim 1, wherein the peak location corresponds to areceived slot boundary.
 9. A method as claimed in claim 1, wherein:calculating the first I results includes FIR filtering the I signalusing a first FIR I-signal filter; calculating the first Q resultsincludes FIR filtering the Q signal using a first FIR Q-signal filter;calculating the second I results includes FIR filtering the I signalusing a second FIR I-signal filter; and calculating the second Q resultsincludes FIR filtering the Q signal using a second FIR Q-signal filter.10. A method as claimed in claim 9, wherein the second FIR I-signalfilter uses 241 taps, instead of 256 taps.
 11. A method as claimed inclaim 1, wherein the method avoids rounding or truncation error causedby averaging.
 12. A method as claimed in claim 1, wherein the first FIRI-signal filter is reused for a secondary synchronization.
 13. A methodas claimed in claim 1, wherein: the first I results and first Q resultsare calculated simultaneously; the I and Q sign bits are obtainedsimultaneously; the second I results and second Q results are calculatedsimultaneously.
 14. A method for slot synchronization for a cell search,using finite impulse response (FIR) filters, the method comprising:receiving an I signal and a Q signal; calculating from a first FIRfiltering of the I and Q signals; obtaining I and Q sign bits from thefirst I and Q results respectively; calculating second I and Q resultsfrom a second FIR filtering of the I and Q signals, using the I and Qsign bits; processing the second I and Q results using an algorithm,thereby providing accumulated results; storing the accumulated resultsfrom the algorithm in a memory; successively processing successivesecond I and Q results from successive second FIR filtering according tothe algorithm, over a same location in different slots to obtainsuccessive accumulated results and storing the successive accumulatedresults in the memory; and searching the successive accumulated resultsfrom the memory for a peak location which corresponds to a slotboundary.
 15. The method of claim 14, wherein the algorithm includes:determining a value equal to the square of a sum of components of theresults from the second I results, and adding the value to the square ofa sum of components of the second Q results.
 16. The method of claim 14,wherein the algorithm includes: determing a magnitude of a sum ofcomponents of the second I results, and adding the magnitude to amagnitude of a sum of a components of the second Q results.
 17. Themethod of claim 14, wherein: wherein calculating the first I resultsincludes FIR filtering the I signal using a first FIR I-signal filter;calculating the second I results includes FIR filtering the I signalusing a second FIR I-signal filter; and the second FIR I-signal filteruses 241 taps, instead of 256 taps.
 18. The method of claim 14, wherein:calculating the first I results includes FIR filtering the I signalusing a first FIR I-signal filter; calculating the first Q resultsincludes FIR filtering the Q signal using a first FIR Q-signal filter;calculating the second I results includes FIR filtering the I signalusing a second FIR I-signal filter; and calculating the second Q resultsincludes FIR filtering the first Q signal using a second FIR Q-signalfilter.
 19. A slot synchronization device, comprising: a first finiteimpulse response (FIR) I-signal filter structured to receive an I signaland produce filtered I results, including an I sign bit; a first FIRQ-signal filter structured to receive a Q signal and produce filtered Qresults, including a Q sign bit; a second FIR I-signal filter structuredto obtain the I sign bit from the first FIR I-signal filter and producesecond filtered I results; a second FIR Q-signal filter structured toobtain the Q sign bit from the first FIR Q-signal filter and producesecond filtered Q results; processing means for processing the secondfiltered I and Q results using an algorithm, thereby providingaccumulated results that are stored in a memory, wherein the processingmeans are structured to successively process successive second filteredI results and successive second filtered Q results according to thealgorithm, over a same location in different slots to obtain successiveaccumulated results and store the successive accumulated results in thememory; and a physical layer processor structured to search thesuccessive accumulated results from the memory for a peak location whichcorresponds to a slot boundary.
 20. The slot synchronization device ofclaim 19, wherein the algorithm includes: determining a value equal tothe square of a sum of components of the second filtered I results, andadding the value to the square of a sum of components of the second Qresults.
 21. The slot synchronization device of claim 19, wherein thealgorithm includes: determining a magnitude of a sum of components ofthe second filtered I results, and adding the magnitude to a magnitudeof a sum of a components of the second filtered Q results.
 22. The slotsynchronization device of claim 19, wherein the second FIR I-signalfilter uses 241 taps, instead of 256 taps.